Cypress Computer Hardware STK16C88 3 User Manual

STK16C88-3  
256 Kbit (32K x 8) AutoStore+ nvSRAM  
Features  
Functional Description  
Fast 35ns Read access and R/W cycle time  
The Cypress STK16C88-3 is a 256Kb fast static RAM with a  
nonvolatile element in each memory cell. The embedded  
Directly replaces battery-backed SRAM modules such as  
Dallas/Maxim DS1230W  
nonvolatile elements incorporate QuantumTraptechnology  
producing the world’s most reliable nonvolatile memory. The  
SRAM provides unlimited read and write cycles, while  
independent, nonvolatile data resides in the highly reliable  
QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile  
memory. Both the STORE and RECALL operations are also  
available under software control.  
Automatic nonvolatile STORE on power loss  
Nonvolatile STORE under Software control  
Automatic RECALL to SRAM on power up  
Unlimited Read/Write endurance  
1,000,000 STORE cycles  
100 year data retention  
Single 3.3V+0.3V power supply  
Commercial and Industrial Temperatures  
28-pin (600 mil) PDIP package  
RoHS compliance  
Logic Block Diagram  
Cypress Semiconductor Corporation  
Document Number: 001-50594 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 29, 2009  
 
STK16C88-3  
If the STK16C88-3 is in a WRITE state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
Device Operation  
The AutoStore+ STK16C88-3 is a fast 32K x 8 SRAM that does  
not lose its data on power down. The data is preserved in integral  
QuantumTrap non-volatile storage elements when power is lost.  
Automatic STORE on power down and automatic RECALL on  
power up guarantee data integrity without the use of batteries.  
and system VCC or between CE and system VCC  
.
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The STK16C88-3 software  
STORE cycle is initiated by executing sequential CE controlled  
READ cycles from six specific address locations in exact order.  
During the STORE cycle, an erase of the previous nonvolatile  
data is first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output are  
disabled until the cycle is completed.  
SRAM Read  
The STK16C88-3 performs a READ cycle whenever CE and OE  
are LOW while WE is HIGH. The address specified on pins A0–14  
determines the 32,768 data bytes accessed. When the READ is  
initiated by an address transition, the outputs are valid after a  
delay of tAA (READ cycle 1). If the READ is initiated by CE or OE,  
the outputs are valid at tACE or at tDOE, whichever is later (READ  
cycle 2). The data outputs repeatedly respond to address  
changes within the tAA access time without the need for transi-  
tions on any control input pins, and remains valid until another  
address change or until CE or OE is brought HIGH.  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence. If they intervene, the  
sequence is aborted and no STORE or RECALL takes place.  
To initiate the software STORE cycle, the following READ  
sequence is performed:  
SRAM Write  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0FC0, Initiate STORE cycle  
A WRITE cycle is performed whenever CE and WE are LOW.  
The address inputs must be stable prior to entering the WRITE  
cycle and must remain stable until either CE or WE goes HIGH  
at the end of the cycle. The data on the common IO pins DQ0–7  
are written into the memory if it has valid tSD, before the end of  
a WE controlled WRITE or before the end of an CE controlled  
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid  
data bus contention on common IO lines. If OE is left LOW,  
internal circuitry turns off the output buffers tHZWE after WE goes  
LOW.  
The software sequence is clocked with CE controlled READs.  
When the sixth address in the sequence is entered, the STORE  
cycle commences and the chip is disabled. It is important that  
READ cycles and not WRITE cycles are used in the sequence.  
It is not necessary that OE is LOW for a valid sequence. After the  
tSTORE cycle time is fulfilled, the SRAM is again activated for  
READ and WRITE operation.  
AutoStore+ Operation  
The STK16C88-3’s automatic STORE on power down is com-  
pletely transparent to the system. The STORE initiation takes  
less than 500 ns when power is lost (VCC<VSWITCH) at which point  
the part depends only on its internal capacitor for STORE com-  
pletion.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations is  
performed:  
If the power supply drops faster than 20 μs/volt before Vcc  
reaches Vswitch, then a 2.2 ohm resistor should be inserted  
between Vcc and the system supply to avoid a momentary  
excess of current between Vcc and internal capacitor.  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0C63, Initiate RECALL cycle  
In order to prevent unneeded STORE operations, automatic  
STOREs are ignored unless at least one WRITE operation has  
taken place since the most recent STORE or RECALL cycle.  
Software initiated STORE cycles are performed regardless of  
whether or not a WRITE operation has taken place.  
Hardware RECALL (Power Up)  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared, and then the nonvolatile information is transferred into  
the SRAM cells. After the tRECALL cycle time, the SRAM is once  
again ready for READ and WRITE operations. The RECALL  
operation does not alter the data in the nonvolatile elements. The  
nonvolatile data can be recalled an unlimited number of times.  
During power up or after any low power condition (VCC<VRESET),  
an internal RECALL request is latched. When VCC once again  
exceeds the sense voltage of VSWITCH, a RECALL cycle is  
automatically initiated and takes tHRECALL to complete.  
Document Number: 001-50594 Rev. **  
Page 3 of 14  
 
STK16C88-3  
Figure 3. Current Versus Cycle Time (WRITE)  
Hardware Protect  
The STK16C88-3 offers hardware protection against  
inadvertent STORE operation and SRAM WRITEs during low  
voltage conditions. When VCAP<VSWITCH, all externally  
initiated STORE operations and SRAM WRITEs are inhibited.  
Noise Considerations  
The STK16C88-3 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF  
connected between VCC and VSS, using leads and traces that  
are as short as possible. As with all high speed CMOS ICs,  
careful routing of power, ground, and signals helps prevent  
noise problems.  
Low Average Active Power  
CMOS technology provides the STK16C88-3 the benefit of  
drawing significantly less current when it is cycled at times  
longer than 50 ns. Figure 2 and Figure 3 shows the  
relationship between ICC and READ or WRITE cycle time.  
Worst case current consumption is shown for both CMOS and  
TTL input levels (commercial temperature range, VCC = 5.5V,  
100% duty cycle on chip enable). Only standby current is  
drawn when the chip is disabled. The overall average current  
drawn by the STK16C88-3 depends on the following items:  
Best Practices  
nvSRAM products have been used effectively for over 15  
years. While ease-of-use is one of the product’s main system  
values, experience gained working with hundreds of applica-  
tions has resulted in the following suggestions as best  
practices:  
1. The duty cycle of chip enable  
2. The overall cycle rate for accesses  
3. The ratio of READs to WRITEs  
4. CMOS versus TTL input levels  
5. The operating temperature  
6. The VCC level  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites will sometimes reprogram these values. Final NV  
patterns are typically repeating patterns of AA, 55, 00, FF,  
A5, or 5A. End product’s firmware should not assume a NV  
array is in a set programmed state. Routines that check  
memory content values to determine first time system config-  
urationand coldor warmboot status, should always program  
a unique NV pattern (for example, complex 4-byte pattern of  
46 E6 49 53 hex or more random bytes) as part of the final  
system manufacturing test to ensure these system routines  
work consistently.  
7. IO loading  
Figure 2. Current Versus Cycle Time (READ)  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a  
preset state, best practice is to again rewrite the nvSRAM  
into the desired state as a safeguard against events that  
might flip the bit inadvertently (program bugs or incoming  
inspection routines).  
Document Number: 001-50594 Rev. **  
Page 4 of 14  
 
   
STK16C88-3  
Table 2. Software STORE/RECALL Mode Selection  
A13 – A0  
Mode  
IO  
Notes  
CE  
L
WE  
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile STORE  
L
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile RECALL  
Notes  
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
2. While there are 15 addresses on the STK16C88-3, only the lower 14 are used to control software modes.  
Document Number: 001-50594 Rev. **  
Page 5 of 14  
 
   
STK16C88-3  
Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V  
Power Dissipation ......................................................... 1.0W  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Operating Range  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature .................................65°C to +150°C  
Temperature under bias..............................55°C to +125°C  
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.5V  
Voltage on Input Relative to Vss............–0.6V to VCC + 0.5V  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
3.0V to 3.6V  
3.0V to 3.6V  
-40°C to +85°C  
DC Electrical Characteristics  
Over the operating range (VCC = 3.0V to 3.6V)  
Parameter  
Description  
Test Conditions  
Min  
Max Unit  
ICC1  
Average VCC Current  
tRC = 35 ns  
Dependent on output loading and cycle rate.  
Values obtained without output loads.  
Commercial  
50  
52  
mA  
mA  
Industrial  
I
OUT = 0 mA.  
ICC2  
ICC3  
Average VCC Current  
during STORE  
All Inputs Do Not Care, VCC = Max  
Average current for duration tSTORE  
3
8
mA  
mA  
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.  
tRC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained  
Typical  
without output loads.  
[3]  
ISB1  
Average VCC Current  
(Standby, Cycling TTL  
Input Levels)  
tRC=35ns, CE > VIH  
Commercial  
Industrial  
18  
19  
mA  
mA  
[3]  
ISB2  
VCC Standby Current  
(Standby, Stable CMOS  
Input Levels)  
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).  
1
mA  
IIX  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
-1  
-1  
+1  
+1  
μA  
μA  
IOZ  
Off State Output  
Leakage Current  
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL  
VIH  
VIL  
Input HIGH Voltage  
2.2  
VCC  
0.5  
+
V
V
Input LOW Voltage  
VSS  
0.5  
0.8  
VOH  
VOL  
Output HIGH Voltage  
Output LOW Voltage  
IOUT = –4 mA  
IOUT = 8 mA  
2.4  
V
V
0.4  
Data Retention and Endurance  
Parameter  
DATAR  
Description  
Min  
100  
Unit  
Years  
K
Data Retention  
NVC  
Nonvolatile STORE Operations  
1,000  
Note  
3. CE > V will not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-50594 Rev. **  
Page 6 of 14  
 
 
STK16C88-3  
Capacitance  
In the following table, the capacitance parameters are listed.[4]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = 0 to 3.0 V  
Max  
5
Unit  
pF  
CIN  
V
COUT  
7
pF  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.[4]  
Parameter  
Description  
Test Conditions  
28-PDIP  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and proce-  
dures for measuring thermal impedance, per EIA /  
JESD51.  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
°C/W  
Figure 4. AC Test Loads  
R1 317Ω  
3.3V  
Output  
R2  
30 pF  
351Ω  
AC Test Conditions  
Input Pulse Levels..................................................0 V to 3 V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels................... 1.5 V  
Note  
4. These parameters are guaranteed by design and are not tested.  
Document Number: 001-50594 Rev. **  
Page 7 of 14  
 
 
STK16C88-3  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
35 ns  
Description  
Chip Enable Access Time  
Unit  
Cypress  
Alt  
Min  
Max  
Parameter  
tACE  
tELQV  
tAVAV, ELEH  
tAVQV  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
t
Read Cycle Time  
35  
[6]  
tAA  
tDOE  
Address Access Time  
35  
15  
tGLQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
[6]  
tOHA  
tAXQX  
5
5
[7]  
[7]  
[7]  
[7]  
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tELQX  
tEHQZ  
13  
13  
35  
tGLQX  
0
0
tGHQZ  
[4]  
tPU  
tELICCH  
tEHICCL  
[3, 4]  
tPD  
Switching Waveforms  
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 6]  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢌꢊ'$7$ꢌ287ꢋ  
'$7$ꢌ9$/,'  
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢌꢊ'$7$ꢌ287ꢋ  
'$7$ꢌ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
5. WE must be HIGH during SRAM Read Cycles.  
6. I/O state assumes CE and OE < V and WE > V ; device is continuously selected.  
IL  
IH  
7. Measured ±200 mV from steady state output voltage.  
Document Number: 001-50594 Rev. **  
Page 8 of 14  
 
     
STK16C88-3  
Table 3. SRAM Write Cycle  
Parameter  
35 ns  
Description  
Unit  
Cypress  
Parameter  
Alt  
Min  
Max  
tWC  
tAVAV  
tWLWH, WLEH  
tELWH, ELEH  
tDVWH, DVEH  
tWHDX, EHDX  
tAVWH, AVEH  
tAVWL, AVEL  
tWHAX, EHAX  
tWLQZ  
tWHQX  
Write Cycle Time  
Write Pulse Width  
35  
25  
25  
12  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPWE  
tSCE  
tSD  
tHD  
tAW  
tSA  
tHA  
tHZWE  
tLZWE  
t
t
Chip Enable To End of Write  
Data Setup to End of Write  
t
t
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
t
25  
0
t
t
0
[7,8]  
13  
5
Switching Waveforms  
Figure 7. SRAM Write Cycle 1: WE Controlled [9]  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 8. SRAM Write Cycle 2: CE Controlled [9]  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
9.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-50594 Rev. **  
Page 9 of 14  
 
   
STK16C88-3  
AutoStorePlus or Power Up RECALL  
STK16C88-3  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
tHRECALL  
tRESTORE  
tHLHZ  
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
ns  
V
tSTORE  
[4, 6]  
tstg  
Power-down AutoStore Slew Time to Ground  
Low Voltage Reset Level  
500  
2.7  
VRESET  
2.4  
VSWITCH  
Low Voltage Trigger Level  
2.95  
V
Switching Waveforms  
Figure 9. AutoStorePlus/Power Up RECALL  
9&&  
ꢆꢎꢆ9  
96:,7&+  
95(6(7  
WVWJ  
$XWR6WRUHŒ  
W6725(  
32:(5ꢍ83 5(&$//  
W+5(&$//  
:(  
'4ꢌꢊ'$7$ꢌ287ꢋ  
%52:1ꢌ287  
$XWR6WRUH3OXVH  
%52:1ꢌ287  
$XWR6WRUH3OXVH  
32:(5ꢍ83ꢌ  
5(&$//  
%52:1ꢌ287  
12 6725(ꢌ'8(ꢌ72  
12ꢌ65$0ꢌ:5,7(6  
12 5(&$//  
ꢊ9&&ꢌ','ꢌ127ꢌ*2ꢌ  
%(/2:ꢌ95(6(7ꢋ  
5(&$//ꢌ:+(1  
12 5(&$//  
ꢊ9&&ꢌ','ꢌ127ꢌ*2ꢌ  
%(/2:ꢌ95(6(7ꢋ  
9
ꢌ5(78516  
&&  
$%29(ꢌ96:,7&+  
Notes  
10. t  
starts from the time V rises above V .  
SWITCH  
HRECALL  
CC  
Document Number: 001-50594 Rev. **  
Page 10 of 14  
 
 
STK16C88-3  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows. [11, 12]  
35 ns  
Parameter  
Alt  
Description  
Unit  
Min  
35  
0
Max  
tRC  
tAVAV  
tAVEL  
tELEH  
tELAX  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
ns  
ns  
ns  
ns  
μs  
[11]  
tSA  
tCW  
Clock Pulse Width  
25  
20  
[7, 11]  
tHACE  
Address Hold Time  
tRECALL  
RECALL Duration  
20  
Switching Waveforms  
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
tSA  
tSCE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).  
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-50594 Rev. **  
Page 11 of 14  
 
   
STK16C88-3  
Part Numbering Nomenclature  
STK16C88 - 3W F 35 I  
Temperature Range:  
Blank - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
35 - 35 ns  
Lead Finish  
F = 100% Sn (Matte Tin)  
Package:  
W = Plastic 28-pin 600 mil DIP  
Ordering Information  
Speed  
Operating  
Range  
Package Diagram  
Package Type  
28-pin PDIP  
(ns)  
Ordering Code  
STK16C88-3WF35  
STK16C88-3WF35I  
35  
51-85017  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts  
Document Number: 001-50594 Rev. **  
Page 12 of 14  
 
STK16C88-3  
Package Diagrams  
Figure 11. 28-Pin (600 Mil) PDIP (51-85017)  
51-85017 *B  
Document Number: 001-50594 Rev. **  
Page 13 of 14  
 
STK16C88-3  
Document History Page  
Document Title: STK16C88-3 256 Kbit (32K x 8) AutoStore+ nvSRAM  
Document Number: 001-50594  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2625096  
GVCH/PYRS  
12/19/08  
New data sheet  
Sales, Solutions and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
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integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-50594 Rev. **  
Revised January 29, 2009  
Page 14 of 14  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  
 

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